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HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
1Gb DDR2 SDRAM
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Oct. 2007 1
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
Revision Details
Rev. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Initial data sheet released Typo corrected Leakage current spec added and IDD value updated Removed improper note in ODT DC spec Added tDS/tDH(single ended strobe) parameter Inserted Pin Description & Adjusted IDD spec values Corrected Typo History Draft Date Mar. 2006 May. 2006 May. 2006 July. 2006 Aug. 2006 Mar. 2007 Oct. 2007
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Contents
1. Description
1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions(SSTL_1.8) 3.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance
4. AC Timing Specifications 5. Package Dimensions
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
* * * * * * * * * * * * * * * * * * * * * * * * * VDD=1.8V +/- 0.1V VDDQ=1.8 +/- 0.1V All inputs and outputs are compatible with SSTL_18 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write(centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 3, 4 and 5 supported Programmable additive latency 0, 1, 2, 3 and 4supported Programmable burst length 4/8 with both nibble sequential and interleave mode Internal eight bank operations with single pulsed RAS Auto refresh and self refresh supported tRAS lockout supported 8K refresh cycles /64ms JEDEC standard 68ball FBGA(x4/x8) , 92ball FBGA(x16) Full strength driver option controlled by EMRS On Die Termination supported Off Chip Driver Impedance Adjustment supported Read Data Strobe supported (x8 only) Self-Refresh High Temperature Entry
Ordering Information
Part No. HY5PS1G431A(L)FP-XX* HY5PS1G831A(L)FP-XX* HY5PS1G1631A(L)FP-XX* Note: Configuration Package 256Mx4 128Mx8 64Mx16 92 Ball 68 Ball
Operating Frequency
Grade E3 C4 Y5 tCK(ns) 5 3.75 3 CL 3 4 5 tRCD 3 4 5 tRP 3 4 5 Unit Clk Clk Clk
XX* is the speed bin, refer to the Operation Frequency table for complete part number. Hynix lead-free products are compliant to RoHS.
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1.2 Pin Configuration & Address Table 256Mx4 DDR2 Pin Configuration(Top view: see balls through package)
1
NC
2 NC
3 A B C D
7
8 NC
9 NC
VDD NC VDDQ NC VDDL
NC VSSQ DQ1 VSSQ VREF CKE
VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC
E F G H J K L M N P R T U V
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
VDDQ NC VDDQ NC VDD ODT
BA2
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size
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256Mx4 8 BA0,BA1,BA2 A10/AP A0 - A13 A0-A9, A11 1 KB
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
128Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package)
1
NC
2 NC
3 A B C D
7
8 NC
9 NC
VDD DQ6 VDDQ DQ4 VDDL
NU/RDQS VSSQ DQ1 VSSQ VREF CKE
VSS DM/RDQS VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC
E F G H J K L M N P R T U V
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
VDDQ DQ7 VDDQ DQ5 VDD ODT
BA2
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size 128Mx8 8 BA0, BA1, BA2 A10/AP A0 - A13 A0-A9 1 KB
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64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
1 NC 2 NC 3 A B C VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE NC, BA2 BA0 A10/AP VSS A3 A7
VDD
7
8 NC
9 NC
VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC, A14
D E F G H J K L M N P R T U V W X
VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC, A15
UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC, A13
VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT
VDD
VSS
A12
NC
NC
AA
NC
NC
ROW AND COLUMN ADDRESS TABLE
ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size
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64Mx16 8 BA0, BA1, BA2 A10/AP A0 - A12 A0-A9 2 KB
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1.3 PIN DESCRIPTION
PIN CK, CK TYPE Input DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS command. Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during MODE REGISTER SET commands. Data input / output : Bi-directional data bus Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals. DQS, (DQS) (UDQS),(UDQS) (LDQS),(LDQS) (RDQS),(RDQS) In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x4 DQS/DQS x8 DQS/DQS if EMRS(1)[A11] = 0 x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1 x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x4 DQS x8 DQS if EMRS(1)[A11] = 0 x8 DQS, RDQS, if EMRS(1)[A11] = 1 8 x16 LDQS and UDQS
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE DM (LDM, UDM)
Input
Input
BA0 - BA2
Input
A0 -A15
Input
DQ
Input/Output
Input/Output
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-ContinuedPIN NC VDDQ VSSQ VDDL VSSDL VDD VSS VREF Supply Supply Supply Supply Supply Supply Supply TYPE DESCRIPTION No Connect : No internal electrical connection is present. DQ Ground DQ Power Supply : 1.8V +/- 0.1V DLL Power Supply : 1.8V +/- 0.1V DLL Ground Power Supply : 1.8V +/- 0.1V Ground Reference voltage for inputs for SSTL interface.
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2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG II Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V) Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100 -2 uA ~ 2 uA Units V V V V C uA Notes 1 1 1 1 1, 2
IOZ
-5 uA ~ 5 uA
uA
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions. Please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol tOPER Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At tOPER 85~95..., Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate. Parameter Operating Temperature Rating 0 to 95 Units C Notes 1,2
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3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Symbol VDD VDDL VDDQ VREF VTT Note: 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V Notes 1 1,2 1,2 3,4 5
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Deviation of VM with respect to VDDQ/2 SYMBOL Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM MIN 60 120 40 -6 NOM 75 150 50 MAX 90 180 60 +6 UNITS NOTES ohm ohm ohm % 1 1 1 1
Note : 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18 VIH (ac) - VIL (ac) I(VIH (ac)) - I(VIL (ac)) Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
Rtt(eff) =
2 x Vm delta VM = VDDQ - 1 x 100%
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3.2.1 Input DC Logic Level
Symbol VIH(dc) VIL(dc) Parameter dc input logic high dc input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
3.2.2 Input AC Logic Level
Symbol VIH (ac) VIL (ac) Parameter ac input logic high ac input logic low DDR2 400,533 Min. VREF + 0.250 Max. VREF - 0.250 DDR2 667,800 Min. VREF + 0.200 Max. VREF - 0.200 Units V V Notes
3.2.3 AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Note: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
VDDQ VIH(ac) min
VSWING(MAX)
VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TF Falling Slew = VREF - VIL(ac) max delta TF
delta TR
Rising Slew = VIH(ac) min - VREF delta TR
< Figure : AC Input Test Signal Waveform>
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3.2.4 Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Note:
Parameter ac differential input voltage ac differential cross point voltage
Min. 0.5 0.5 * VDDQ - 0.175
Max. VDDQ + 0.6 0.5 * VDDQ + 0.175
Units Notes V V 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Note: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
Crossing point
VIX or VOX
3.2.5 Differential AC output parameters
Symbol VOX (ac) Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations1. in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Notes 1
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3.3.1 Output AC Test Conditions
Symbol VOTR Note: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 Class II 0.5 * VDDQ Units V Notes 1
3.3.2 Output DC Current Drive
Symbol IOH(dc) IOL(dc) Note: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
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3.3.3 OCD default characteristics
Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications ( Toper; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUTVDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions. Output Slew rate load:
VTT
Parameter
Min 0 0
Nom -
Max 1.5 4
Unit ohms ohms ohms V/ns
Notes 1 6 1,2,3 1,4,5,6,7,8
Sout
1.5
-
5
25 ohms
Output (Vout)
Reference point
7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
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3.4 IDD Specifications & Test Conditions IDD Specifications(max)
Symbol x4 IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 Normal IDD6 Low power F S 80 95 10 25 35 35 35 60 150 160 260 10 5 260 DDR2 400 x8 80 95 10 25 35 35 35 60 150 160 260 10 5 260 x16 110 130 10 25 35 35 35 60 200 200 260 10 5 390 x4 85 100 10 28 40 35 35 65 170 180 260 10 5 295 DDR2 533 x8 85 100 10 28 40 35 35 65 170 180 260 10 5 295 x16 115 135 10 28 40 35 35 65 220 220 260 10 5 420 x4 90 105 10 30 45 38 38 72 210 220 270 10 5 310 DDR2 667 x8 90 105 10 30 45 38 38 72 210 220 270 10 5 310 x16 120 140 10 30 45 40 40 72 260 260 270 10 5 430 x4 100 115 10 32 50 38 38 75 240 250 270 10 5 340 DDR2 800 Units x8 100 115 10 32 50 38 38 75 240 250 270 10 5 340 x16 130 150 10 32 50 40 40 75 290 290 270 10 5 480 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
IDD7
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(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); Fast PDN Exit MRS(12) = 0 CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1 Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Units mA
IDD1
mA
IDD2P IDD2Q IDD2N
mA mA mA mA mA mA
IDD3P
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
IDD7
mA
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Note : 1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade) 2. IDD specifications are tested after the device is properly initialized 3. Input slew rate is specified by AC Parametric Test Condition 4. IDD parameters are specified with ODT disabled. 5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11.
6. Definitions for IDD
LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
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DDR2-667 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD)-x4/x8 tRRD(IDD)-x16 tCK(IDD) tRASmin(IDD) tRASmax(IDD) tRP(IDD) tRFC(IDD)-256Mb tRFC(IDD)-512Mb tRFC(IDD)-1Gb tRFC(IDD)-2Gb 5-5-5 5 15 60 7.5 9 3 45 70000 15 75 105 127.5 197.5 6-6-6 6 18 63 7.5 9 3 45 70000 18 75 105 127.5 197.5 DDR2-533 4-4-4 4 15 60 7.5 10 3.75 45 70000 15 75 105 127.5 197.5 5-5-5 5 18.75 63.75 7.5 10 3.75 45 70000 18.75 75 105 127.5 197.5 DDR2-400 3-3-3 3 15 55 7.5 10 5 40 70000 15 75 105 127.5 197.5 4-4-4 4 20 65 7.5 10 5 45 70000 20 75 105 127.5 197.5 Units tCK ns ns ns ns ns ns ns ns ns ns ns ns
Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Timing Patterns for 4 bank devices x4/ x8/ x16 -DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D -DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D -DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D -DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D Timing Patterns for 8 bank devices x4/8 -DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7 -DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D Timing Patterns for 8 bank devices x16 -DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D -DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
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3.5. Input/Output Capacitance
DDR2 400 DDR2 533 Min Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS CCK CDCK CI CDI CIO CDIO 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 4.0 0.5 DDR2 667 DDR2 800 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 3.5 0.5 pF pF pF pF pF pF
Parameter
Symbol
Units
4. Electrical Characteristics & AC Timing Specification
( 0 TCASE 95; VDDQ = 1.8 +/- 0.1V; VDD = 1.8 +/- 0.1V)
Refresh Parameters by Device Density
Parameter Refresh to Active/ Refresh command time Average periodic refresh interval tREFI Symbol tRFC 0 TCASE 85 85 TCASE 95 256Mb 75 7.8 3.9 512Mb 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb 327.5 7.8 3.9 Units ns us us
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRPNote1 tRAS tRC DDR2-667 4-4-4 min 4 12 12 45 57 DDR2-533 3-3-3 min 3 11.25 11.25 45 56.25 DDR2-533 4-4-4 min 4 15 15 45 60 DDR2-533 5-5-5 min 5 18.75 18.75 45 63.75 DDR2-400 3-3-3 min 3 15 15 40 55 DDR2-400 4-4-4 min 4 20 20 40 65 tCK ns ns ns ns Units
Note 1: 8 bank device Precharge All Allowance : tRP for a Precharge All command for and 8 Bank device will equal to tRP+1*tCK, where tRP are the values for a single bank Precharge, which are shown in the above table.
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Timing Parameters by Speed Grade
Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time(differential strobe) DQ and DM input hold time(differential strobe) DQ and DM input setup time(single ended strobe) DQ and DM input hold time(single ended strobe) Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK
Symbol
DDR2-400 min max
+600 +500 0.55 0.55 -
DDR2-533 min
-500 -450 0.45 0.45 min(tCL, tCH) 3750 100 225 -25 -25 0.6 0.35 tAC min
Unit
Note
max
+500 +450 0.55 0.55 ps ps tCK tCK ps 11,12
tAC tDQSCK tCH tCL tHP
-600 -500 0.45 0.45 min(tCL, tCH) 5000 150 275 25 25 0.6 0.35 tAC min
tCK tDS(base) tDH(base) tDS tDH tIPW tDIPW tHZ tLZ (DQS) tLZ (DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIS tIH tRPRE tRPST
8000 tAC max tAC max
8000 tAC max tAC max
ps ps ps ps ps tCK tCK ps ps
15 6,7,8,20 6,7,8,21 6,7,8,20 6,7,8,21
18 18
DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble
2*tAC min
tAC max
2*tAC min
tAC max
ps
18
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 350 475 0.9 0.4
350 450 WL + 0.25 0.6 1.1 0.6
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 250 375 0.9 0.4
300 400 WL + 0.25 0.6 1.1 0.6
ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns
13 12
10
5,7,9,23 5,7,9,23
Active to active command period for 1KB page size products Active to active command period for 2KB page size products
tRRD
7.5
-
7.5
-
4
tRRD
10
-
10
-
ns
4
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Parameter Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on Symbol DDR2-400 min tFAW 37.5 max DDR2-533 min 37.5 max ns
Unit
Note
tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
tCKE tAOND t
50 2 15 WR+tRP* 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+ 2 2.5 tAC(min) tAC(min)+ 2 3 8 0 tIS+tCK+tI H
-
50 2
tCK ns tCK ns ns ns tCK tCK tCK tCK tCK 2 tAC(max) +1 2tCK+tAC (max)+1 2.5 tAC(max) + 0.6 2.5tCK+tA C(max)+1 tCK ns 16 1 1, 2 14 24 3
-
15 WR+tRP* 7.5 7.5 tRFC + 10
-
200 2 2 6 - AL 3
2 tAC(max)+ 1 2tCK+ tAC(max) +1 2.5 tAC(max)+ 0.6 2.5tCK+tA C(max)+1
2 tAC(min) tAC(min)+ 2 2.5 tAC(min) tAC(min)+ 2 3 8
AON
ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW
tAONPD
ns tCK ns ns tCK tCK 17
t
AOFD
tAOF
t
AOFPD tANPD tAXPD tOIT tDelay
12
0 tIS+tCK+tI H
12
ns ns 15
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Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS
Symbol
tAC tDQSCK tCH tCL tHP tCK tDS(base) tDH(base) tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH
DDR2-667 min
-450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 200 275 0.9 0.4 45 7.5 10 37.5 50 2 15 WR+tRP -
DDR2-800 min
-400 -350 0.45 0.45 min(tCL, tCH) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 175 250 0.9 0.4 45 7.5 10 37.5 50 2 15 WR+tRP tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 70000 -
Unit
ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns ns tCK ns tCK
Note
max
+450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 + 0.25 0.6 1.1 0.6 70000 -
max
+400 +350 0.55 0.55 -
11,12 15 6,7,8,20 6,7,8,21
18 18 18 13 12
First DQS latching transition to associated clock edge tDQSS DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIS(base) tIH(base) tRPRE tRPST tRAS tRRD tRRD tFAW tFAW tCCD tWR tDAL
10
5,7,9,22 5,7,9,23 19 19 3 4 4
14
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-ContinueDDR2-667 min
tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
t t t
Parameter
Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW
Symbol
7.5 7.5
DDR2-800 min
7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 2 tAC(min) tAC(min) +2 2.5 tAC(min) tAC(min) +2 3 8 12 0 tIS+tCK +tIH 12 2 tAC(max) +0.7 2tCK+ tAC(max)+1 2.5 tAC(max) +0.6 2.5tCK+ tAC(max)+1 -
Unit
ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns
Note
max
-
max
-
3
tRFC + 10 200 2 2 7 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min) +2 3 8 0 tIS+tCK+tIH
1 1, 2
CKE AOND AON
tAC(max) +0.7 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1
6,16
tAONPD t
AOFD
tAOF t
17
AOFPD
tANPD tAXPD tOIT tDelay
15
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General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 2. DDR2 SDRAM AC timing reference load The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ DQS DQS RDQS RDQS
DUT
Output Timing reference point 25
VTT = VDDQ/2
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown below.
VDDQ DUT
DQ DQS, DQS RDQS, RDQS
Output Test point 25
VTT = VDDQ/2
Slew Rate Test Load
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4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
DQS
tDQSH
tDQSL
DQS/ DQS
DQS tWPRE VIH(ac) VIH(dc) D VIL(ac) tDS tDS VIH(ac) DMin VIL(ac) tDH DMin D D VIL(dc) tDH DMin VIL(dc) VIH(dc) D tWPST
DQ
DM
DMin
Figure -- Data input (write) timing
tCH CK
tCL
CK/CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
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Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. AL = Additive Latency 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System Derating for other slew rate values. 8. tDS and tDH derating
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table) DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4
tD tD tD tD tD tD tD tD tD tD tD tD tD tD tD tD tD tD S H S H S H S H S H S H S H S H S H 125 45 125 45 +125 +45 83 0 21 0 83 0 -11 21 0 -14 +83 0 -11 -25 -43 -67 +21 0 -14 -31 -54 -83 95 12 1 -13 -31 33 12 -2 -19 -42 24 13 -1 -42 -43 24 10 -7 -19 -59 25 11 -7 -31 -74 22 5 -8 -47 -89 23 5 -19 -62 17 -6 -35 -77 17 -7 -50 6 -23 -65 5 -38 -11 -53
-110 -125 -175 -188
-127 -140 -115 -128 -103 -116
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating value listed in Table x. Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ` VREF(dc) to ac region', use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc) max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
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HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP Fig. a. Illustration of nominal slew rate for tIS,tDS
CK,DQS CK, DQS tIS, tDS VDDQ tIH, tDH tIS, tDS tIH, tDH
VIH(ac)min
VIH(dc)min
nominal slew rate
VREF(dc) nominal slew rate VREF to ac region
VIL(dc)max
VIL(ac)max Vss
Delta TF Setup Slew Rate = Falling Signal VREF(dc)-VIL(ac)max Delta TF
Delta TR Setup Slew Rate = Rising Signal VIH(ac)min-VREF(dc) Delta TR
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HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP Fig. b. Illustration of tangent line for tIS,tDS
CK, DQS CK, DQS tIS, tDS VDDQ nominal line VIH(ac)min tIH, tDH tIS, tDS tIH, tDH
VIH(dc)min tangent line VREF(dc) Tangent line VIL(dc)max VREF to ac region VIL(ac)max Nomial line Vss Delta TF
Delta TR Setup Slew Rate Tangent line[VIH(ac)min-VREF(dc)] = Rising Signal Delta TR
Setup Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Falling Signal Delta TF
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HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP Fig. c. Illustration of nominal line for tIH, tDH
CK, DQS CK, DQS tIS, tDS VDDQ tIH, tDH tIS, tDS tIH, tDH
VIH(ac)min
VIH(dc)min dc to VREF region VREF(dc) nominal slew rate nominal slew rate
VIL(dc)max
VIL(ac)max
Vss Delta TR Hold Slew Rate = Rising Signal VREF(dc)-VIL(dc)max Delta TR Delta TF
VIH(dc)min - VREF(dc) Hold Slew Rate = Falling Signal Delta TF
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HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP Fig. d. Illustration of tangent line for tIH , tDH
CK, DQS CK, DQS
tIS, tDS
VDDQ
tIH, tDH
tIS, tDS
tIH, tDH
VIH(ac)min nominal line VIH(dc)min tangent line VREF(dc) dc to VREF region VIL(dc)max Tangent line nominal line
VIL(ac)max
Vss Delta TR Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Rising Signal Delta TR Tangent line[VIH(ac)min-VREF(dc)] Hold Slew Rate = Falling Signal Delta TF Delta TF
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9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values CK, CK Differential Slew Rate 2.0 V/ns tIS
4.0 3.5 3.0 2.5 2.0 1.5 1.0 +187 +179 +167 +150 +125 +83 +0 -11 -25 -43 -67 -100 -150 -223 -250 -500 -750 -1250
1.5 V/ns tIS
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1.0 V/ns tIS
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
tIH
+94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125
tIH
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
tIH
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Command / 0.8 Address Slew 0.7 rate(V/ns) 0.6
0.5 0.4 0.3 0.25 0.2 0.15 0.1
0.9
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating value listed in above Table. Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc to VREF(dc) region', use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.7 / Oct. 2007 32
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces. 12. t QH = t HP - t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle. 14. t DAL = (nWR) + ( tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the t WR parameter stored in the MRS. Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks. 15. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet.
Rev. 0.7 / Oct. 2007
33
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
VOH + xmV VOH + 2xmV tHZ tRPST end point VOL + 1xmV VOL + 2xmV VTT -xmV VTT - 2xmV VTT + 2xmV VTT + xmV tHZ tRPRE begin point
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS tDS tDH tDS tDH
VDDQ VIH(ac)min VIH(dc)min VREF(dc) VIL(dc)max VIL(ac)max VSS
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. 23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test.
Rev. 0.7 / Oct. 2007 34
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
5. Package Dimensions
Package Dimension(x4,x8)
68Ball Fine Pitch Ball Grid Array Outline
11.00 0.10
A1 BALL MARK
17.50 0.10
< Top View>
< SIDE View>
0.80 X 8 = 6.40 2.10 0.10 A1 BALL MARK
987 A B C D E F G H J K L M N P R 321
0.15 0.05
2-R0.13MAX
1.10 0.10 0.34 0.05
0.80
1.60 1.60
W
68X 0.45 0.05
0.80
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.7 / Oct. 2007 35
0.80 X 18 = 14.40
HY5PS1G431A(L)FP HY5PS1G831A(L)FP HY5PS1G1631A(L)FP
Package Dimension(x16)
92Ball Fine Pitch Ball Grid Array Outline
11.00 0.10
A1 BALL MARK
17.50 0.10
< Top View>
0.80 X 8 = 6.40 2.10 0.10
< SIDE View>
0.15 0.05
2-R0.13MAX
1.10 0.10 A1 BALL MARK
987 A B C D E F G H J K L M N P R T U V W X AA 1.60 1.60 321
0.34 0.05
0.80 0.80
68X 0.45 0.05
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.7 / Oct. 2007
36
0.80 X 20 = 16.00

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